This invention relates to an instruction prefetching device for use in a data processing system.
A data processing system usually includes an instruction prefetching device. Various instruction prefetching devices are already known. For example, an instruction prefetching device is revealed in U.S. patent application Ser. No. 552,223 filed Nov. 16, 1983, now abandoned, by Syuichi Hanatani et al including Toshiteru Shibuya, the present applicant, for assignment to the present assignee. The referenced application was filed as a continuation-in-part application on Dec. 19, 1988 of U.S. patent application Ser. No. 286,021, now issued U.S. Pat. No. 4,984,154 on Jan. 8, 1991. According to the Hanatani et al application, the instruction prefetching device is for successively prefetching each of program instructions as a prefetched instruction before an instruction executing circuit of the data processing system executes a current instruction prefetched earlier than the prefetched instruction.
The instruction prefetching device comprises an instruction memory circuit assigned with real instruction addresses and divided into a plurality of page frames for memorizing the program instructions as memorized instructions. The program instructions generally include branch instructions. The real instruction addresses are held in an instruction address register one at a time as a prefetched real instruction address which belongs to one of the page frames that is used as a prefetch page frame. The real instruction address register accesses the instruction memory circuit to produce one of the memorized instructions from the prefetch real instruction address as the prefetched instruction.
The instruction prefetching device carries out a branch prediction by using a branch history table (BHT). The branch history table memorizes branch address specifying signals which specify real instruction addresses of the branch instructions as branch instruction addresses and branch destination addresses predicted by prior results of execution of the respective branch instructions. When the prefetch real instruction address coincides with a particular one of the branch instruction addresses that is specified by one of the branch address specifying signals, the branch history table produces a BHT (branch history table) hit signal and a particular one of the branch destination addresses that corresponds to the particular branch instruction address as a predicted branch destination address. Responsive to the BHT hit signal, an instruction prefetch control circuit controls a request address selector to make the request address selector supply the instruction address register with the predicted branch destination address which next follows the prefetch real instruction address. Otherwise, the instruction prefetch control circuit controls the request address selector to make the request address selector supply the instruction address register with a next real instruction address which is equal to a sum of the prefetch real instruction address and a read-out width.
As known in the art, program instructions are stored in a virtual storage at successive virtual instruction addresses, namely, successive pages assigned with successive page numbers. However, the program instructions are stored in a real storage (the instruction memory circuit) at discontinuous real instruction addresses, namely, discontinuous page frames assigned with discontinuous page frame numbers. More specifically, the program instructions include page last instructions, each of which is located at an end of a page frame. The page last instruction is followed by a page-over instruction located at a top of another page frame which does not always follow the page frame for the page last instruction in question. In other words, the other page frame for the page-over instruction has a page frame number which is not always equal to that obtained by adding one to another page frame number of the page frame for the page last instruction in question.
That is, a particular page last instruction is indicated by a particular page last real instruction address which belongs to a particular page frame assigned with a particular page frame number. The particular page last instruction is followed by a next succeeding page-over instruction indicated by a specific page-over real instruction address belonging to a specific page frame assigned with a specific page frame number which does not always follow the particular page frame number.
When the prefetch real instruction address coincides with the particular page last instruction without coincidence of the current real instruction address with any branch instruction addresses, the specific page frame number must be calculated in order to prefetch the next succeeding page-over instruction. In other words, prefetch of instruction is not continued when the prefetch real instruction address coincides with one of the page last instructions without coincidence of the prefetch real instruction address with any branch instruction addresses. This is because a change is made as regards a page frame number of a page frame to which a real instruction address of the next following instruction to be prefetched belongs as a result which is obtained by an addition of the prefetch real instruction address and the read-out width. Such a change of the page frame number is called a page-over. On occurrence of the page-over, the prefetch of instruction must be carried out by the real instruction address which belongs to the page frame assigned with the page frame number corresponding to the page number obtained by adding one to the page number in correspondence to the page frame number to which the prefetch real instruction address belongs.
In order to process the page-over, a conventional instruction prefetching device such as that disclosed by Hanatani et al, prefetches the page last instruction as the prefetched instruction from the instruction memory circuit at the page last real instruction address held in the instruction address register. The page last instruction is decoded into a decoded signal by an instruction decoding circuit. Responsive to the decoded signal, an instruction address generating circuit generates a virtual instruction address of the next succeeding page-over instruction which should next be prefetched. The virtual instruction address is translated to a real instruction address of the next succeeding page-over instruction by an instruction address translating circuit. The real instruction address is held in the instruction address register under control of the instruction prefetch control circuit to make the instruction memory circuit produce the next succeeding page-over instruction. Therefore, the conventional instruction prefetching device wastes a lot of time on processing of the page-over. That is, the conventional instruction prefetching device results in degradation of performance of the data processing system.